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EEPROM rotation for ESP8266 and ESP32

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naked-esp12-624x416

Xose Pérez over at Tinkerman writes:

The Arduino Core for ESP8266 and ESP32 uses one SPI flash memory sector to emulate an EEPROM. When you initialize the EEPROM object (calling begin) it reads the contents of the sector into a memory buffer. Reading a writing is done over that in-memory buffer. Whenever you call commit it write the contents back to the flash sector.
Due to the nature of this flash memory (NOR) a full sector erase must be done prior to write any new data. If a power failure (intended or not) happens during this process the sector data is lost.
Also, writing data to a NOR memory can be done byte by byte but only to change a 1 to a 0. The only way to turn 0s to 1s is to perform a sector erase which turns all memory positions in that sector to 1. But sector erasing must be done in full sectors, thus wearing out the flash memory faster.

How can we overcome these problems?

Full details at tinkerman.cat.


BUS PIRATE: first test of Ultra v1b with SPI EEPROM

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Bus Pirate prototype “Ultra” v1b successfully wrote to and read back from a 25LC020A SPI EEPROM chip. The image shows the Bus Pirate reading 8 bytes of 0x02 from the EEPROM at address 0x00, and the bus activity can be verified on the logic analyzer graph. Still a long way to go, but it’s nice to have everything working.

Tomorrow we’ll finish the major SPI commands and general purpose mode features like analog measurement and manipulation of the auxiliary pins. As always, you can follow our latest progress in the forum.

App note: Implementation of error code correction in EEPROMs

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App note from ON Semiconductors about their EEPROM error correction. Link here (PDF)

Some of ON’s automotive EEPROMs, like the Grade 0 NV25xxx family (SPI, 1 – 64 Kb) and the Grade 1 CAV24Cxx / CAV25xxx (Grade 1, 128 Kb and higher) implement an Error Code Correction scheme. What this means is that for each chunk of data in the EEPROM array (8 bits for 1 – 64 Kb densities, 32 bits for 128 Kb and higher), the memory stores a redundancy code in separate EEPROM cells.

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